1. Field of the Invention
The present invention relates to a semiconductor memory having column selection lines which are wired in common to plural memory blocks and redundancy circuits that relieve from failures.
2. Description of the Related Art
In general, semiconductor memories such as DRAMs have not only real memory cells but also redundancy circuits such as redundancy memory cells in order to increase the yield by taking relief measures against failures due to crystal defects in a semiconductor substrate, particles introduced during a fabrication process, and the like. More specifically, for example, redundancy word lines (row redundancy circuit) that replace word lines and redundancy bit lines (column redundancy circuit) that replace bit lines are formed in each memory block.
Patent document 1 discloses a technique that increases the efficiency of relief from failures in a semiconductor memory having a pair of memory blocks using redundancy circuits. That is, relief from a failure in one memory block is attained by using a redundancy word line or a redundancy bit line of the other memory block. However, in this technique, it is necessary to form a column decoder for each memory block. Further, since a row block address is used in selecting a real bit line, the column decoders become large and fuse circuits for column redundancy become large, which results in increase in chip size.
Patent document 2 and Non-patent document 1 disclose examples of semiconductor memories that can relieve failures in one memory block by using a redundancy circuit of the other memory block, in which plural column redundancy circuits are formed so as to correspond to respective memory groups each having a prescribed number of memory blocks and have redundancy column selection lines that are common to plural memory blocks. In this kind of semiconductor memory, the chip size can be reduced because of the common use of a column decoder. Further, by using the common redundancy column selection lines, bit line failures and the like can have relief attained on a memory block basis.
Patent document 1: Japanese Internal Publication No. 2002-512416
Patent document 2: Japanese Unexamined Patent Application Publication No. 2003-16795
Non-patent document 1: Kiyohiro FURUTANI, Takeshi HAMAMOTO, Takeo MIKI, Masaya NAKANO, Takashi KONO, Shigeru. KIKUDA, Yasuhiro KONISHI, and Tsutomu YOSHIHARA, “Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories,” IEICE TRANS. ELECTRON., Vol. E88-C, No. 2, February 2005
However, in Patent document 2, relief for word line (row redundancy) can be attained only in a pair of memory blocks. In other words, a word line cannot attain relief by using the redundancy circuit of an arbitrary memory block. Therefore, when, for example, failures caused by a large particle occur in one memory block in a concentrated manner, there may not be enough redundancy circuits relieving those failures. In this case, the relief efficiency lowers and hence the yield lowers.
In Non-patent document 1, redundancy word lines are formed in only one of a pair of memory blocks. The bit lines are longer and the load capacitance of each bit line is larger in the memory block having the redundancy word lines than in the memory block not having the redundancy word lines. Therefore, the access time is longer in the memory block having the redundancy word lines than in the memory block not having the redundancy word lines. That is, the electric characteristic during an access operation is worse when the structures of the memory blocks differ.
Among conventional semiconductor memories in which plural column redundancy circuits are formed so as to correspond to respective memory groups each having a prescribed number of memory blocks and to have redundancy column selection lines that are common to plural memory blocks, there have been no semiconductor memories in which the memory blocks have the same structure and can relieve failures occurred in a certain memory block by using the redundancy circuit of an arbitrary memory block. In other words, to solve the above problems at the same time, it is necessary to provide a special column redundancy selection circuit that selects a redundancy column selection line (column redundancy circuit). However, no such column redundancy selection circuits have been proposed.